Features, operation principle and limits of SPI and I2C communication protocols for smart objects: a novel SPI-based hybrid protocol especially suitable for IoT applications

The Internet of Things (IoT) is an expression, sometimes abused by companies given the absence of an unambiguous meaning, that indicates the upcoming evolution of Internet as it has been known so far. In fact, all objects will have network capabilities which will be exploited to overcome, in certain situations, human intervention. Thanks to the direct cooperation of new class of devices, aware of their operating scenario and interconnected in subnetworks, our life style will be strongly enhanced and simplified. IoT, however, is not yet the “El Dorado” of technology, capable of revolutionizing everyday life: some aspects and open issues have to be carefully analyzed. The huge complexity of this new technology forces companies to select a specific research field: for this reason, they focus only on some features that an IoT device should have to guarantee fulfillment of requirements. In this context, this research work concerns an analysis of features, operation principle and limits of SPI and I2C communication protocols followed by the proposal of a new hybrid protocol suited for embedded systems, named FlexSPI, thought as an evolution of the classic SPI. Thanks to a robust software architecture, it is able to provide many features that can be used by smart objects to enhance their capabilities. In this way, sensors and actuators or, more in general, subsystems, can quickly exchange data and efficiently react to malfunctioning; moreover, number of devices on bus can be safely increased even while smart object is performing operations

Impact of Scaling on CMOS Radio Frequency Class-E Power Amplifiers

Although technological scaling is benefical for CMOS ICs for digital applications, it impacts seriously on analog and radio frequency circuit performances. In this scenario, this paper investigates power loss mechanisms in Class-E power amplifiers highlighting their depedencies on technological scaling. An analytical model describing PA power added efficiency is obtained, and its results are validated against circuit simulations. Scaling effects on efficiency are modeled and discussed, showing that Class-E PA performance are not significantly affected by scaling when delivering low-medium output power, contrarily to what is commonly believed

A 1.4GHz \u2013 2GHz Wideband CMOS Class-E Power Amplifier Delivering 22dBm peak with 67% PAE

The design of CMOS power amplifiers (PA) is still a challenging issue. Efficiency is one of the key requirements, but it is usually obtained at the expense of large device stress. The latter can be reduced by introducing a cascode solution, which features an efficiency penalty due to dissipative mechanisms associated with MOS capacitive parasitics, overlooked up to date. A class-E PA is proposed which allows simultaneously high efficiency and reduced stress by means of an integrated inductor tuning out the parasitic. Prototypes, realized in a 0.13 \u3bcm CMOS technology, demonstrate 67% PAE while delivering 23 dBm peak power at 1.7 GHz. PAE is still above 60% within the range 1.4-2 GHz

A 1.7GHz 31dBm differential CMOS Class-E Power Amplifier with 58% PAE

This paper shows that CMOS Class-E PAs are capable of high Power-Added Efficiency (PAE), even when delivering large output powers at Radio Frequency (RF). In particular, a cascode device is used to obtain high efficiency while assuring reliable operation. A differential solution has been adopted to maximize 2nd harmonic suppression and minimize potential on-chip interference. Prototypes realized in 0.13μm CMOS technology using thick oxide devices show the following performances: 31dBm maximum output power at 1.7GHz with 67% drain efficiency and 58% PAE, -51dBc and -39.5dBc suppression for 2nd and 3rd harmonics, respectively.This paper shows that CMOS Class-E PAs are capable of high Power-Added Efficiency (PAE), even when delivering large output powers at Radio Frequency (RF). In particular, a cascode device is used to obtain high efficiency while assuring reliable operation. A differential solution has been adopted to maximize 2nd harmonic suppression and minimize potential on-chip interference. Prototypes realized in 0.13mu;m CMOS technology using thick oxide devices show the following performances: 31dBm maximum output power at 1.7GHz with 67% drain efficiency and 58% PAE, -51dBc and -39.5dBc suppression for 2nd and 3rd harmonics, respectively

Oxide Breakdown After RF Stress: Experimental Analysis and Effects on Power Amplifier Operation

The target in the design of CMOS radio-frequency (RF) transceivers for wireless application is the highest integration level, despite reliability issues of conventional submicron MOSFETs, due to high RF voltage and current peaks. In this scenario, this paper investigates gate-oxide breakdown under RF stress by using a class-E power amplifier (PA) for experiments. We showed that maximum RF voltage peaks for safe device operation are much larger than usual DC limits, and that the physical mechanism of oxide degradation is triggered by the rms value of oxide field, and not by its maximum, as generally believed. This finding has a strong impact on RF circuit designs, especially in MOSFET scaling perspectives. Finally, breakdown effects on PA operations are discussed

Operation principle, advanced procedures and validation of a new Flex-SPI communication Protocol for smart IoT devices

In this paper, we report on hardware structure, operation mode and software development for a new advanced communication protocol whose aim is obtaining a fully shared SPI bus with a fixed amount of wires, without renouncing to advantages of a push-pull output stage and obtaining an architecture capable of great flexibility. All four signals of a classic SPI protocol are entirely shared by the slaves on bus: when a master wants to communicate with a particular device, it will perform an addressing at packet level: starting from its main characteristics, various adopted solutions to realize a shared SPI bus will be analyzed, explaining how a communication session is performed. The firmware structure was designed as a software stack composed by interacting layers, tracing model of similar protocols that share with FlexSPI some features. Some of the advanced procedures that can be performed thanks to this protocol will be discussed, highlighting the suitability of FlexSPI for dynamic smart objects; in fact, by adding these features to developed framework, it is possible to explore and appreciate expandability of this communication protocol, making it suitable to meet advanced IoT requirements of smart objects. FlexSPI can be built like a MAC layer above the SPI bus, to process all necessary pieces of information to perform the packet level addressing, using a stack having a layered architecture. This is idea followed in the firmware development, to implement this communication protocol, experimentally verified in the performed and reported communication tests, confirming that it is possible to obtain a shared push-pull bus

FRAMEWORK IMPLEMENTATION, FIRMWARE DEVELOPMENT AND CHARACTERIZATION OF FLEX-SPI COMMUNICATION PROTOCOL: ENERGY CONSUMPTION ANALYSIS AND COMPARISON WITH I2C STANDARD

In this paper, we report a detailed description of developed Flex-SPI firmware structure together with experimental tests carried out by using ad-hoc instrumental setups based on TI MSP-EXP430F5438 experimenter boards. Developed framework, aimed to provide a solid base to test the possibility of performing a shared SPI communication with a fixed number of wires without renouncing to push-pull output stage advantages, has been implemented and successfully validated. Also, FlexSPI energy consumption has been evaluated and then compared with the I2C one, by proper experimental setups and related data processing: the two protocols, in fact, share several features, although they rely on a different hardware configuration. The energy/bit metric was chosen so that the two output stages can be compared regardless the effective quantity of exchanged packets; thus, this measure provides an indication of necessary energy amount to move a single bit to guarantee the correct firmware functionality. Despite larger quantity of exchanged data due to channel reservation needs (with a 35% traffic overhead, in the performed tests), the FlexSPI total energy consumption is comparable with the I2C one, at the same communication speed; thus a lower energy/bit requirement is required for FlexSPI protocol, decreasing with the negotiated speed, in this way proving FlexSPI protocol as a suited and valid choice for high-speed low-consumption communications inside embedded systems with a developed architecture capable of great flexibility

Investigating Flow Dynamics with Wireless Pressure Sensors Network

Wireless sensors networks enable the chance to investigate with enhanced freedom physical phenomena, aiming to increase the informative content obtained by sensors measurements. In this work we will focus on a system allowing to experimentally measure pressure profiles obtained from sensor nodes deployed on a NACA0012 aircraft wing model. By exploiting measurements gathered from sensors, allowing to measure pressure fluctuations of ±600Pa with a resolution of 4Pa, together with results obtained by Computational Fluid Dynamics (CFD) models, the system enables extracting flow profile, thus obtaining information on flow separation and stall phenomenon. Wireless measures are delivered with an enhanced version of IEEE802.15.4e, allowing to decrease power consumption by a factor of 7. Packet routing, based on Routing Protocol for Low-Power and Lossy Networks (RPL), has been improved by means of a newly introduced Lifetime and Latency Aggregatable Metric (L2AM) leading to a 18% increased network lifetime